![]() This is less than #1 and hence the correct cycle adjust. Data launched at 18ns and captured at 20ns. This gives 0ns as candidate but its not accepted as cycle adjust, throw this out too.Ĥ. Data launched at 12ns and captured at 12ns. This gives 6ns as candidate but since we already have lesser value from #1, throw it out.ģ. Data launched at 6ns and captured at 12ns. Data launched at 0ns and captured at 4ns. Cycle adjust calculation is what is shown how it is calculated. Its ofcourse not a full clock cycle, neither is it half of 6 ns or 8ns clock. Next, you gotta figure out what the cycle adjust is between the two clocks. The reason that the figure has waveform drawn for 24ns is because the LCM of 6 and 8 is 24. ![]() Let's not get all delusional instead lets stick to the given facts. Also, the two clocks are in phase, c'mon see the edges lining up at 0 and then 12ns and again at 24ns. Launch flop is rise edge triggered and capture flop is Falling edge triggered. ![]() One thing most people here are confusing is that both the FFs are not positive edge triggered. I think we can still check timing for these two flops. There's a lot of info out there about clock-domain crossing, synchronizers, etc. If the input rate were the slower one then it would be a different story (but still messy). I suggest you either add a FIFO or a multi-cycle constraint. Thus, the output of the B FF after the B rising edge at time 8 will be the SECOND data bit from A the first one never gets clocked into B. But at time 6, NEW data will be clocked out to the D input of B. Using your timing diagram above, after the first A clock edge data will appear at the D input of the B ff. There's no way (that I'm aware of) that you can guaranteed the exact timing of the output of the second ff. However, if this is a critical path then you're going to have to add a synchronizer or FIFO. Is this an FPGA or ASIC design? If so, then depending on the specifics of this circuit you may want to give it a relaxed constraint (like a multi-cycle or ignore). You can't really check this for timing-it's indeterminate (even if you know all the propagation delays, etc) because of the non-integer relationship between the two clocks.
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